SPC564A80L7CFAR

SPC564A80L7CFAR
32-bit MCU, built on the embedded Power Architecture, 4MB Flash, 192 KB SRAM, 3xeSCI, 3xCAN, 3xSPI, ADC, LQFP176, STM, RoHS

The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).

Features:

• 150 MHz e200z4 Power Architecture core
• dV/dt immunity ± 50 V/nsec in full temperature range
• Memory organization4 MB on-chip flash memory with ECC and Read While Write (RWW)192 KB on-chip RAM with standby functionality (32 KB) and ECC8 KB instruction cache (with line locking), configurable as 2- or 4-way
• Configurable interrupt controller (with NMI)64-channel DMA
• 1 × eTPU2 (second generation eTPU)
• 2 enhanced queued analog-to-digital converters (eQADCs)
• On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
• On-chip FMPLL (frequency-modulated phase-locked loop)

Download:

• Datasheet