Introduction to Digital Design/VHDL

Introduction to Digital Design - Richard E. Haskell & Darrin M. Hanna

This book uses 30 examples to show you how to get started designing digital circuits in VHDL or Verilog and using block diagrams, simulate them, and quickly and easily download them to your Basys™ or Nexys2™ board. Get up and running quickly - step-by-step, by example!

A major revolution in digital design has taken place over the past decade. Field programmable gate arrays (FPGAs) can now contain over a million equivalent logic gates and tens of thousands of flip-flops. This means that it is not possible to use traditional methods of logic design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates. The reality is that today digital systems are designed by writing software in the form of hardware description languages (HDLs). The most common HDLs used today are VHDL and Verilog. Both are in widespread use. When using these hardware description languages the designer typically describes the behavior of the logic circuit rather than writing traditional Boolean logic equations. Computer-aided design tools are used to both simulate the VHDL or Verilog design and to synthesize the design to actual hardware.

This book assumes no previous knowledge of digital design. We will use Active-HDL from Aldec to design, simulate, synthesize, and implement our digital designs. A free student edition of Active-HDL simulator is available from Aldec Inc (www.aldec.com). o synthesize your design to a Spartan3E FPGA, you will need to download the Free ISE WebPACK from Xilinx Inc.(www.xilinx.com). The Xilinx synthesis tools are called from within the Aldec Active-HDL integrated GUI. We will use the ExPort utility to download your synthesized design to the Spartan3E FPGA. ExPort is part of the Adept software suite that you can download free from Digilent, Inc.




Important Notes on Software and Hardware Versions

To program a Basys2 or Nexys2 board, you must use a "front end" design tool to create a source file that defines the intended circuit, and "back end" tools to synthesize the source file and download it to the board. Xilinx's free Webpack software contains all needed tools, including source file editors, a synthesizer, and downloader. Aldec also produces a free front-end tool that can be used to create source files. Called Active-HDL, this front-end design tool presents a more student-friendly design interface, and it can automatically route design files to Xilinx's back-end tools. The authors recommend Active-HDL due to its more intuitive interface.

If you are using a Basys board, you must use the user constraints file (.ucf) file for the Basys board (basys.ucf) available at http://www.lbebooks.com/downloads.htm

If you are using a Basys2 board, you must use the user constraints file (.ucf) file for the Basys2 board (basys2board.ucf) available at http://www.lbebooks.com/downloads.htm and you must download the Adept 2.1 (or above) software from the Adept Software page.

You cannot use Adept 1.10 with the Basys2 board.

Table of Contents:

• Example 1 - Switches and LEDs
• Example 2 - 2-Input Gates
• Example 3 - Multiple-Input Gates
• Example 4 - Equality Detector
• Example 5 - 2-to-1 Multiplexer
• Example 6 - Quad 2-to-1 Multiplexer
• Example 7 - 4-to-1 Multiplexer
• Example 8 - Clocks and Counters
• Example 9 - 7-Segment Decoder
• Example 10 - 7-Segment Displays
• Example 11 - 2's Complement 4-Bit Saturator
• Example 12 - Full Adder
• Example 13 - 4-Bit Adder
• Example 14 - N-Bit Adder
• Example 15 - N-Bit Comparator
• Example 16 - Edge-Triggered D Flip-Flop
• Example 17 - D Flip-Flops
• Example 18 - Divide-by-2 Counter
• Example 19 - Registers
• Example 20 - N-Bit Register
• Example 21 - Shift Registers
• Example 22 - Ring Counters
• Example 23 - Johnson Counters
• Example 24 - Debounce Pushbuttons
• Example 25 - Clock Pulse
• Example 26 - Arbitrary Waveform
• Example 27 - Pulse-Width Modulation (PWM)
• Example 28 - Controlling the Position of a Servo
• Example 29 - Scrolling the 7-Segment Display
• Example 30 - Fibonacci Sequence
• Appendix A - Aldec Active-HDL Tutorial
• Appendix B - Number Systems
• Appendix C - Basic Logic Gates
• Appendix D - Boolean Algebra and Logic Equations
• Appendix E - VHDL/Verilog Quick Reference Guide

Download:

• Click here to download (VHDL Edition)
• Click here to download (Verilog Edition)

Manufacturer: Digilent
Code: 593-002