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Basics of designing logic circuits and computers
ID: 47240
Mano M. Morris, Kime Charles R.
The manual is devoted to the design of digital circuits and systems. It consists of three parts. The first part presents the structure of a classical computer and the basic concepts related to the representation and processing of information. The second part discusses, among others, main elements of Boolean algebra, ways of representation of logic functions and their implementation, combinational and sequential circuits as well as methods of describing their operation, including using VHDL and Yerilog languages, typical functional blocks, programmable logic structures and microprogrammed control. The third part is devoted to the elements of the computer system, including central units with the RISC and CISC architecture. At the end of each chapter there is a summary of the messages contained therein, a bibliography and a set of tasks for self-solution.
The manual is intended for students of electronics, telecommunications and computer science at technical universities. It will benefit from lectures and exercises in such subjects as: electronic circuits, digital technology, computer systems design.
A few comments from the translator
Preface
1.1. Digital computers
The way of representing information
Computer structure
More about a general purpose computer
1.2. Numerical systems
Binary numbers
Octal and hexadecimal numbers
Numerical ranges
1.3. Arithmetic operations
Conversion of decimal numbers to other counting systems
1.4. Decimal codes
Add numbers in the BCD code
Parity bit
1.5. Gray codes
1.6. Alphanumeric codes
ASCII character codes
1.7. Summary
Literature
Works
2.1. Two-valued logic and logic gates
Two-valued logic
Logic gates
2.2. Boolean algebra
Basic identities of Boolean algebra
Algebraic transformations
Complementing the function
2.3. Standard forms of Boolean expressions
Mintermy and maxtermy
The sum of products
The product of sums
2.4. Optimization of two-level systems
The criterion of the cost of implementation
Karnaugh boards for two variables
Karnaugh's table for three variables
Karnaugh's table for four variables
2.5. Transformations of Karnaugh boards
Significant simple implants
Unimportant simple implies
Optimization of the sum of sums
Negligible states (unspecified)
2.6. Optimization of multi-level systems
2.7. Other types of goals
2.8. Operator and EXOR gates
Parity control function
2.9. High impedance outputs
2.10.Podsumowanie
Literature
Works
3.1. Design concepts and automation of the design process
Project hierarchy
Descending project (top down)
Computer-aided design
Hardware description languages
Logical synthesis
3.2. Design space
Properties of goals
Degrees of merge
Systems manufacturing technologies
Technological parameters
Positive and negative logic
Compromising design solutions
3.3. Design procedure
3.4. Selection and implementation in technology
Cell specification
Libraries
Techniques of selection and implementation in a specific technology
3.5. Verification
Manual analysis of logic circuits
Simulation
3.6. Programmable technologies for the implementation of logic circuits
Memory only for reading (ROM)
Programmable PLA type logic modules
Programmable PAL logic matrices
3.7. Summary
Literature
Works
4.1. Combination systems
4.2. Elementary logic functions
Forcing a fixed value, moving and inverting the signal
Features of many bits
Permission operations
4.3. decoders
Expansion of set-top boxes
Connecting the decoder with the permission inputs
4.4. Coders (encoders)
Priority coder
Expansion of encoders
4.5. Selection of signals
Multiplexers
Expansion of multiplexers
Alternative methods for the implementation of the selection function
4.6. Implementation of combinational functions
The use of decoders to implement functions
The use of multiplexers for the implementation of functions
The use of ROM permanent memories to implement functions
Application of programmable logic modules (PLA)
to implement the function
Application of programmable logic matrices (PAL) for the implementation of functions
The use of remembering cells to implement functions
4.7. Presentation of combinational circuits in hardware description languages - VHDL language
4.8. Presentation of combinational circuits in hardware description languages - Verilog language
4.9. Summary
Literature
Works
5.1. Literational combination systems
5.2. Binary adders
Półsumator
Full adder
Cascade adder
Combiner with simultaneous (anticipated) transfers
5.3. Binary subtraction
Completing the numbers
Subtraction using number supplements
5.4. Binary adders - sub-factors
Binary numbers with a sign
Addition and subtraction of binary numbers with a sign
Overflow (excess)
5.5. Binary multiplication
5.6. Other arithmetic functions
System reduction
Bumping
Decrements
Multiplication by fixed values
Dividing by fixed values
Zero completion and expansion
5.7. System representation in hardware description languages - VHDL language
Behavioral description
5.8. System representation in hardware description languages - Verilog language
Behavioral description
5.9. Summary
Literature
Works
6.1. Definitions of sequential circuits
6.2. Latch systems
Click-type systems SR and SR
D-type latching system
6.3. Latches
Master-slave type flip-flops
Flip-flops
Standard graphic symbols
Direct inputs
Time dependencies of the trigger
6.4. Analysis of sequential circuits
Input equations
Passage and exit boards
Status graph
Time dependencies in a sequential system
Simulation
6.5. Designing sequential circuits
Design procedure
Finding state graphs and transition and exit tables
Assign binary combinations to states
Designing with the use of D triggers
Designing using unused states
Verification
6.6. Other types of latches
JK and T flip-flops
6.7. Presentation of sequential circuits in hardware description languages
- VHDL language
6.8. Presentation of sequential circuits in hardware description languages
- Verilog language
6.9. Chapter summary
Literature
Works
7.1. Registers and permission for parallel entry
Register with parallel entry
7.2. Inter-register transfers
7.3. Transactions between registers
7.4. Information only for VHDL and Verilog language users
7.5. microoperations
Arithmetic microoperations
Logical microoperations
Displacement micro-operations (data)
7.6. Microoperations on a single register
Data transfer based on the use of multiplexers
Shift registers
Cascade counter
Synchronous binary counters
Other counters
7.7. Designing of register cells
7.8. Inter-register transitions in layouts of many registers using
from multiplexers and buses
Three-state busses
7.9. Serial transmissions and microoperations
Serial addition
7.10. Presenting shift registers and counters in the description languages
equipment - VHDL language
7.11. Presenting shift registers and counters in the description languages
equipment - Verilog language
7.12. Summary
Literature
Works
8.1. Control unit
8.2. Algorithmic state machines
ASM diagrams
Considerations regarding time dependencies
8.3. Examples of ASM diagrams
Binary multiplying system
8.4. System control using fixed connections
Sequence register and decoder
Method one trigger for one state
8.5. Presentation of a binary multiplier in hardware description languages
- VHDL language
8.6. Presentation of a binary multiplication system in the description languages
equipment - Verilog language
8.7. Microprogrammed control
8.8. Summary
Literature
Works
9.1. Memory definitions
9.2. Memory of free access
Write and read operations
Time runs
Memory properties
9.3. SRAM memory integrated circuits
Coincidence diagram of memory cells selection
9.4. Matrix of SRAM memory integrated circuits
9.5. DRAM memory integrated circuits
DRAM memory cell
DRAM bit of DRAM memory
9.6. Types of DRAM memory
Synchronous DRAM (SDRAM)
SDRAM with dual data transfer speed (DDR SDRAM)
RAMBUS® DRAM (RDRAM) memory
9.7. Matrix of dynamic memory integrated circuits
9.8. Summary
Literature
Works
10.1. Introduction
10.2. Data paths
10.3. The arithmetic and logic unit
Arithmetic system
Logic system
The arithmetic and logic unit
10.4. Moving system
Cyclic shifting system
10.5. Data path representation
10.6. Control word
10.7. Simple computer architecture
List of orders architecture
Memory resources
Order formats
Order specifications
10.8. System control in one cycle
Decoder of orders
Examples of orders and program
Problems occurring in a computer with one cycle
10.9. System control in many clock cycles
Design of a sequential control system
10.10. Summary
Literature
Works
11.1. Computer architecture concepts
The basic cycle of computer operations
Set of registers
11.2. Addressing arguments
Orders with three addresses
Orders with two addresses
Orders with one address
Orders that do not contain addresses
Addressing architecture
11.3. Addressing modes
Implicit mode
Immediate mode
Register and intermediate register mode
Direct addressing mode
Indirect addressing mode
Relative addressing mode
Index addressing mode
Summary of addressing modes
11.4. List of orders architecture
11.5. Orders to send data
Orders to perform stack operations
Entry and exit orders: independent and mapped by memory
11.6. Operations orders on data
Arithmetic orders
Logical commands and executing actions on bits
Move orders
11.7. Floating point calculations
Arithmetic operations
Exponent moved
Standard argument format
11.8. Program control commands
Orders for conditional branching
Orders calling procedure and return
11.9. Aborting the program
Types of interrupts
Processing of external interrupts
Summary
Literature
Works
12.1. Data path with pipelining
Performing torrential micro operations
12.2. Controlling pipelining
Programming and speed of the pipe work
12.3. A computer with a reduced list of commands
List of orders architecture
Addressing modes
Organization of the data path
Organization of control
Data gambling
Control Hazards
12.4. A computer with a complex list of orders
Modifications to the list of orders
Modifications to the data path
Modifications of the control unit
Microprogrammed control system
Microprograms that execute complex orders
12.5. More information about design
Concepts of very fast central units
The latest innovations in the field of architectures
Digital systems
12.6. Summary
Literature
Works
13.1. Computer input-output devices
13.2. Examples of peripheral devices
Keyboard
Hard drive
Graphic display
I / O transfer rates
13.3. Input-output interfaces
I / O bus and interfaces
Examples of I / O interfaces
Transmission with gating (strobing)
Transmission with reconciliation (confirmation)
13.4. Serial communication
Asynchronous transmission
Synchronous transmission
Once again about the keyboard
A serial I / O bus based on packet transmission
13.5. Transmission modes
Examples of program-controlled transmissions
Transfer initiated by means of an interrupt
13.6. Priority interruptions
Priority daisy chain
Parallel priority system
13.7. Direct access to memory
DMA driver
DMA transfer
13.8. I / O processors
13.9. Summary
Literature
Works
14.1. Hierarchy of memory
14.2. Reference locality
14.3. Cache
Mapping to cache
Row size
Writing data to the cache
Record methods
A combination of all concepts
Command and data caches
Multilevel caches
14.4. Virtual memory
Page tables
Address translation buffer
Virtual memory and cache
14.5. Summary
Literature
Works
List of abbreviations used in the text
Index
The manual is intended for students of electronics, telecommunications and computer science at technical universities. It will benefit from lectures and exercises in such subjects as: electronic circuits, digital technology, computer systems design.
Table of Contents
A few comments from the translator
Preface
Chapter 1: DIGITAL COMPUTERS and INFORMATION
1.1. Digital computers
The way of representing information
Computer structure
More about a general purpose computer
1.2. Numerical systems
Binary numbers
Octal and hexadecimal numbers
Numerical ranges
1.3. Arithmetic operations
Conversion of decimal numbers to other counting systems
1.4. Decimal codes
Add numbers in the BCD code
Parity bit
1.5. Gray codes
1.6. Alphanumeric codes
ASCII character codes
1.7. Summary
Literature
Works
Chapter 2: COMBINATIVE LOGIC ARRANGEMENTS
2.1. Two-valued logic and logic gates
Two-valued logic
Logic gates
2.2. Boolean algebra
Basic identities of Boolean algebra
Algebraic transformations
Complementing the function
2.3. Standard forms of Boolean expressions
Mintermy and maxtermy
The sum of products
The product of sums
2.4. Optimization of two-level systems
The criterion of the cost of implementation
Karnaugh boards for two variables
Karnaugh's table for three variables
Karnaugh's table for four variables
2.5. Transformations of Karnaugh boards
Significant simple implants
Unimportant simple implies
Optimization of the sum of sums
Negligible states (unspecified)
2.6. Optimization of multi-level systems
2.7. Other types of goals
2.8. Operator and EXOR gates
Parity control function
2.9. High impedance outputs
2.10.Podsumowanie
Literature
Works
Chapter 3: DESIGN OF COMBINATED LOGIC SYSTEMS
3.1. Design concepts and automation of the design process
Project hierarchy
Descending project (top down)
Computer-aided design
Hardware description languages
Logical synthesis
3.2. Design space
Properties of goals
Degrees of merge
Systems manufacturing technologies
Technological parameters
Positive and negative logic
Compromising design solutions
3.3. Design procedure
3.4. Selection and implementation in technology
Cell specification
Libraries
Techniques of selection and implementation in a specific technology
3.5. Verification
Manual analysis of logic circuits
Simulation
3.6. Programmable technologies for the implementation of logic circuits
Memory only for reading (ROM)
Programmable PLA type logic modules
Programmable PAL logic matrices
3.7. Summary
Literature
Works
Chapter 4: FUNCTIONS AND LOGIC COMBINATION EXAMPLES
4.1. Combination systems
4.2. Elementary logic functions
Forcing a fixed value, moving and inverting the signal
Features of many bits
Permission operations
4.3. decoders
Expansion of set-top boxes
Connecting the decoder with the permission inputs
4.4. Coders (encoders)
Priority coder
Expansion of encoders
4.5. Selection of signals
Multiplexers
Expansion of multiplexers
Alternative methods for the implementation of the selection function
4.6. Implementation of combinational functions
The use of decoders to implement functions
The use of multiplexers for the implementation of functions
The use of ROM permanent memories to implement functions
Application of programmable logic modules (PLA)
to implement the function
Application of programmable logic matrices (PAL) for the implementation of functions
The use of remembering cells to implement functions
4.7. Presentation of combinational circuits in hardware description languages - VHDL language
4.8. Presentation of combinational circuits in hardware description languages - Verilog language
4.9. Summary
Literature
Works
Chapter 5: FUNCTIONS AND ARRANGEMENTS
5.1. Literational combination systems
5.2. Binary adders
Półsumator
Full adder
Cascade adder
Combiner with simultaneous (anticipated) transfers
5.3. Binary subtraction
Completing the numbers
Subtraction using number supplements
5.4. Binary adders - sub-factors
Binary numbers with a sign
Addition and subtraction of binary numbers with a sign
Overflow (excess)
5.5. Binary multiplication
5.6. Other arithmetic functions
System reduction
Bumping
Decrements
Multiplication by fixed values
Dividing by fixed values
Zero completion and expansion
5.7. System representation in hardware description languages - VHDL language
Behavioral description
5.8. System representation in hardware description languages - Verilog language
Behavioral description
5.9. Summary
Literature
Works
Chapter 6: SEQUENTIAL SYSTEMS
6.1. Definitions of sequential circuits
6.2. Latch systems
Click-type systems SR and SR
D-type latching system
6.3. Latches
Master-slave type flip-flops
Flip-flops
Standard graphic symbols
Direct inputs
Time dependencies of the trigger
6.4. Analysis of sequential circuits
Input equations
Passage and exit boards
Status graph
Time dependencies in a sequential system
Simulation
6.5. Designing sequential circuits
Design procedure
Finding state graphs and transition and exit tables
Assign binary combinations to states
Designing with the use of D triggers
Designing using unused states
Verification
6.6. Other types of latches
JK and T flip-flops
6.7. Presentation of sequential circuits in hardware description languages
- VHDL language
6.8. Presentation of sequential circuits in hardware description languages
- Verilog language
6.9. Chapter summary
Literature
Works
Chapter 7: REGISTRIES AND INTERREGRADE MESSAGES
7.1. Registers and permission for parallel entry
Register with parallel entry
7.2. Inter-register transfers
7.3. Transactions between registers
7.4. Information only for VHDL and Verilog language users
7.5. microoperations
Arithmetic microoperations
Logical microoperations
Displacement micro-operations (data)
7.6. Microoperations on a single register
Data transfer based on the use of multiplexers
Shift registers
Cascade counter
Synchronous binary counters
Other counters
7.7. Designing of register cells
7.8. Inter-register transitions in layouts of many registers using
from multiplexers and buses
Three-state busses
7.9. Serial transmissions and microoperations
Serial addition
7.10. Presenting shift registers and counters in the description languages
equipment - VHDL language
7.11. Presenting shift registers and counters in the description languages
equipment - Verilog language
7.12. Summary
Literature
Works
Chapter 8: SEQUENCE AND CONTROL
8.1. Control unit
8.2. Algorithmic state machines
ASM diagrams
Considerations regarding time dependencies
8.3. Examples of ASM diagrams
Binary multiplying system
8.4. System control using fixed connections
Sequence register and decoder
Method one trigger for one state
8.5. Presentation of a binary multiplier in hardware description languages
- VHDL language
8.6. Presentation of a binary multiplication system in the description languages
equipment - Verilog language
8.7. Microprogrammed control
8.8. Summary
Literature
Works
Chapter 9: BASE OF SEMICOLAR MEMORY
9.1. Memory definitions
9.2. Memory of free access
Write and read operations
Time runs
Memory properties
9.3. SRAM memory integrated circuits
Coincidence diagram of memory cells selection
9.4. Matrix of SRAM memory integrated circuits
9.5. DRAM memory integrated circuits
DRAM memory cell
DRAM bit of DRAM memory
9.6. Types of DRAM memory
Synchronous DRAM (SDRAM)
SDRAM with dual data transfer speed (DDR SDRAM)
RAMBUS® DRAM (RDRAM) memory
9.7. Matrix of dynamic memory integrated circuits
9.8. Summary
Literature
Works
Chapter 10: BASIC DESIGNS FOR COMPUTERS
10.1. Introduction
10.2. Data paths
10.3. The arithmetic and logic unit
Arithmetic system
Logic system
The arithmetic and logic unit
10.4. Moving system
Cyclic shifting system
10.5. Data path representation
10.6. Control word
10.7. Simple computer architecture
List of orders architecture
Memory resources
Order formats
Order specifications
10.8. System control in one cycle
Decoder of orders
Examples of orders and program
Problems occurring in a computer with one cycle
10.9. System control in many clock cycles
Design of a sequential control system
10.10. Summary
Literature
Works
Chapter 11: ARCHITECTURE LIST OF ORDERS
11.1. Computer architecture concepts
The basic cycle of computer operations
Set of registers
11.2. Addressing arguments
Orders with three addresses
Orders with two addresses
Orders with one address
Orders that do not contain addresses
Addressing architecture
11.3. Addressing modes
Implicit mode
Immediate mode
Register and intermediate register mode
Direct addressing mode
Indirect addressing mode
Relative addressing mode
Index addressing mode
Summary of addressing modes
11.4. List of orders architecture
11.5. Orders to send data
Orders to perform stack operations
Entry and exit orders: independent and mapped by memory
11.6. Operations orders on data
Arithmetic orders
Logical commands and executing actions on bits
Move orders
11.7. Floating point calculations
Arithmetic operations
Exponent moved
Standard argument format
11.8. Program control commands
Orders for conditional branching
Orders calling procedure and return
11.9. Aborting the program
Types of interrupts
Processing of external interrupts
Summary
Literature
Works
Chapter 12: RISC and CISC CENTRAL UNITS
12.1. Data path with pipelining
Performing torrential micro operations
12.2. Controlling pipelining
Programming and speed of the pipe work
12.3. A computer with a reduced list of commands
List of orders architecture
Addressing modes
Organization of the data path
Organization of control
Data gambling
Control Hazards
12.4. A computer with a complex list of orders
Modifications to the list of orders
Modifications to the data path
Modifications of the control unit
Microprogrammed control system
Microprograms that execute complex orders
12.5. More information about design
Concepts of very fast central units
The latest innovations in the field of architectures
Digital systems
12.6. Summary
Literature
Works
Chapter 13: ENTRY AND EXIT CONTROL AND COMMUNICATION
13.1. Computer input-output devices
13.2. Examples of peripheral devices
Keyboard
Hard drive
Graphic display
I / O transfer rates
13.3. Input-output interfaces
I / O bus and interfaces
Examples of I / O interfaces
Transmission with gating (strobing)
Transmission with reconciliation (confirmation)
13.4. Serial communication
Asynchronous transmission
Synchronous transmission
Once again about the keyboard
A serial I / O bus based on packet transmission
13.5. Transmission modes
Examples of program-controlled transmissions
Transfer initiated by means of an interrupt
13.6. Priority interruptions
Priority daisy chain
Parallel priority system
13.7. Direct access to memory
DMA driver
DMA transfer
13.8. I / O processors
13.9. Summary
Literature
Works
Chapter 14: MEMORY SYSTEMS
14.1. Hierarchy of memory
14.2. Reference locality
14.3. Cache
Mapping to cache
Row size
Writing data to the cache
Record methods
A combination of all concepts
Command and data caches
Multilevel caches
14.4. Virtual memory
Page tables
Address translation buffer
Virtual memory and cache
14.5. Summary
Literature
Works
List of abbreviations used in the text
Index
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Mano M. Morris, Kime Charles R.