Digital Design / Verilog (593-000)

Book - Digital Design - Richard E. Haskell & Darrin M. Hanna - EDU

"Digital Design using Digilent FPGA Boards" 2nd Edition, 2012
Written by Richard E. Haskell & Darrin M. Hanna

This book uses over 75 examples to show you how to create digital circuits in VHDL or Verilog, simulate them, and quickly and quickly download them to your Basys ™ or Nexys2 ™ board. Get up and running quickly from the basics to the 7-segment display, memory, VGA port, PS / 2 port, and more - step-by-step, by example!

A major revolution in digital design has taken place over the past decade. Field programmable gate arrays (FPGAs) can now contain thousands of flip flops. Diagrams: The digital circuit has to contain thousands of gates. Reality The languages languages languages languages (HDLs). The most common HDLs used today are VHDL and Verilog. Both are in widespread use. These When using hardware description language of the designer typically describes the behavior of the logic circuit rather than writing traditional Boolean logic equations. Computer-aided design tools are used to simulate the VHDL or Verilog design and to synthesize the design to actual hardware.

This book assumes no previous knowledge of digital design. You can learn about basic gates, logic equations, Boolean algebra, and Karnaugh maps. In over 75 examples we use VHDL or Verilog to simulate, and synthesize the designs of a Xilinx Spartan3E FPGA on either the Basys or Nexys2 ™ FPGA board. A free student edition of Active-HDL simulator is available from Aldec Inc. ( www.aldec.com ). To synthesize your design to a Spartan3E FPGA, you will need to download the Free ISE WebPACK from Xilinx Inc. ( www.xilinx.com ). The XilinX synthesis tools are available in the Aldec Active-HDL integrated GUI. We will use the ExPort utility to download your synthesized design to the Spartan3E FPGA. ExPort is part of the Adept software suite that you can download free from Digilent, Inc.

Important Notes on Software and Hardware Versions
This is a program a Basys2 or Nexys2 board, you must use a "front end", a tool to create a source file. Xilinx's free Webpack software contains all the necessary tools, including source file editors, a synthesizer, and downloader. Aldec also produces a free front-end tool that can be used to create source files. Called Active-HDL, this front-end design tool presents a more student-friendly design interface, and it can automatically route design files to Xilinx's back-end tools. The authors recommend Active-HDL due to its more intuitive interface.

If you are using a Basys board, you must use the user constraints file (.ucf) file for the Basys board (basys.ucf) available at http://www.lbebooks.com/downloads.htm

If you are using a Basys2 board, you must use the user constraints file (.ucf) file for the Basys2 board (basys2board.ucf) available at http://www.lbebooks.com/downloads.htm and you must download the Adept 2.1 (or above) software from the Adept Software page.

You can not use Adept 1.10 with the Basys2 board.

Table of Contents:

• 1. Introduction
• 2. Basic Logic Gates
• 3. Boolean Algebra and Logic Equations
• 4. Implementing Digital Circuits
• 5. Combinational Logic
• 6. Arithmetic Circuits
• 7. Sequential Logic
• 8. Finite State Machines
• 9. Datapaths and Control Units
• 10. Integrating the Datapath and Control Unit
• 11. Memory
• 12. VGA Controller
• 13. PS / 2 Port
• Appendix A - Aldec Active-HDL Tutorial
• Appendix B - Number Systems
• Appendix C - Making a Turnkey System
• Appendix D - VHDL / Verilog Quick Reference Guide
• Appendix E - Installing the Xilinx ISE / WebPACK, Aldec Active-HDL, and Digilent Adept2 Software
• Appendix F - VHDL / Verilog Quick Reference Guide

Manufacturer: Digilent
Code: 593-000