Programmable signal and information processing circuits

A clear lecture in the field of designing digital signal processing systems, including the latest issues of logic synthesis, structural synthesis, hardware specification languages (VHDL, Verilog) and hierarchical design methods with particular emphasis on programmable PLD / FPGA chips. The substantive value of the book raises the description of advanced logic synthesis procedures supporting commercial design systems and enabling efficient reduction of hardware resources necessary for the implementation of digital circuits in PLD / FPGA structures.

Table of Contents:

From authors 8
1. PRELIMINARY INFORMATION 9
1.1. General information 9
1.2. The role of programmable systems in the development of digital technology for signal and information processing 10
1.3. The specificity of designing digital circuits in FPGA structures 12
Literature to chapter 1 14

2. PROGRAMMABLE SYSTEMS 17
2.1. Introduction 17
2.2. ALTERA 20 systems
2.2.1. MAX 20 systems
2.2.2. FLEX 24 systems
2.2.3. Cyclone II systems 27
2.2.4. Stratix II 28 systems
2.3. XILINX 31 systems
2.3.1. SPARTAN 31 systems
2.3.2. Virtex II systems 36
Literature to chapter 2 38


3. ADVANCED PROCEDURES FOR LOGIC SYNTHESES 40
3.1. Introduction 40
3.2. Argument reduction and parallel decomposition 41
3.3. Functional decomposition - classic method 48
3.4. Functional decomposition using the division method method 51
3.4.1. Serial decomposition - basic model 51
3.4.2. The concept of r-fitness and inseparable inseparation 57
3.4.3. Balanced decomposition 63
3.5. Synthesis of sequential circuits in FPGA structures with embedded blocks of memory 68
Literature to chapter 3 75


4. SYNTHESIS OF DIGITAL ARRANGEMENTS 79
4.1. Basic information 79
4.2. Numeric codes 80
4.3. Functional blocks 82
4.3.1. Introductory information 82
4.3.2. Multiplexers and demultiplexers 83
4.3.3. Arithmetic systems 86
4.3.4. Registers and counters 90
4.3.5. Mains 94
4.3.6. Memory 95
4.4. Parameters of functional blocks 96
4.5. Structural synthesis 101
4.6. Synthesis example - BIN2BCD 104 converter
4.7. Microprogrammed systems 107
4.8. Decoders of microinstructions 113
Literature to chapter 4 115


5. LANGUAGES OF DESCRIPTION OF EQUIPMENT 116
5.1. General information 116
5.2. The language of VHDL 118
5.2.1. General information 118
5.2.2. Objects and data types 121
5.2.3. Packages and libraries 124
5.2.4. Language instructions for VHDL 124
5.2.5. Modeling at the structural level 139
5.3. The language Verilog 141
5.3.1. General information 141
5.3.2. Code documentation 142
5.3.3. Data, numbers, parameters 143
5.3.4. Operators 146
5.3.5. Module 149
5.3.6. Continuous assignments 150
5.3.7. Procedural assignments 151
5.3.8. Structural designs 153
5.3.9. Sequential systems 153
5.3.10. Testing program 156
Literature to chapter 5 158


6. DESIGNING WITH THE USE OF HDL 160 LANGUAGES
6.1. Introduction 160
6.2. Converting with the "+3" method 160
6.3. Structural implementation of data flow 161
6.4. RTL design methodology 165
6.5. Implementation of conversion "+3" using the RTL 167 methodology
6.6. Application of the pipeline concept 185
6.7. Application of advanced algorithms of logic synthesis 190
6.8. Comparison of implementation results 197
Literature to chapter 6 199


7. DESIGN OF DSP 200 SYSTEMS
7.1. General information 200
7.2. Basic operations of DSP 201
7.3. Distributed arithmetic 205
7.4. Digital filters with finite impulse response 212
7.4.1. Introductory information 212
7.4.2. Programmable FIR 213 filter
7.4.3. FIR filter with fixed coefficients of 217
7.4.4. FIR filter with inverted structure 223
7.4.5. FIR filter with distributed arithmetic 226
7.5. Transformation systems 236
Literature to chapter 7 240


8. DESIGN OF CRYPTOGRAPHIC SYSTEMS 241
8.1. Introduction 241
8.2. The DES 241 algorithm
8.2.1. Construction of the 242 algorithm
8.2.2. Implementation of elementary transformations of the DES 244 algorithm
8.2.3. Iterative implementation of the DES 253 algorithm
8.2.4. Combination of the DES 260 algorithm
8.2.5. Pipelization of the DES 264 algorithm
8.2.6. Comparison of implementation results 267
8.3. The hash function 268
8.3.1. General information 268
8.3.2. Description of the Whirlpool 269 function
8.3.3. Hardware implementation 270
8.3.4. Experimental results 273
Literature to chapter 8 277


ACCESSORIES 278
D1. BASIC MATHEMATICAL CONCEPTS 278
D2. SHORT DESCRIPTION SPECIFICATIONS 282
SKOROWIDZ 296