GT8UB256M8BN

SDDR DDR3 2Gb, 1.5V memory

Description:

The 2Gb Double-Data-Rate-3 (DDR3) B-die DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I / Os x 8 banks or 16Mbit x 16 I / Os x 8 bank devices. These synchronous devices achieve high speed double-data-rates transfer rates up to 1600 Mb / sec / pin for general applications. Chip key chip key chip The D D D D D D D D D D. DDR3 DRAM key features. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I / Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

Features:

• 1.5V ± 0.075V (JEDEC Standard Power Supply)
• 8 Internal memory banks (BA0- BA2)
• Differential clock input (CK, CK)
• Programmable CAS Latency: 6, 7, 8, 9, 10, 11
• CAS WRITE Latency (CWL): 5,6,7,8
• POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2
• Programmable Sequential / Interleave Burst Type
• Programmable Burst Length: 4, 8
• 8n-bit prefetch architecture
• Output Driver Impedance Control
• Differential bidirectional data strobe
• Write Leveling
• OCD Calibration
• Dynamic ODT (Rtt_Nom & Rtt_WR)
• Self-Refresh
• Self-Refresh Temperature
• RoHS Compliance
• Package: 78-Ball BGA
• Operating temperature Commerical grade (0 ℃ ≦ TC ≦ 95 ℃)

Memory pinout: