Verification Techniques for System-Level Design

This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue is to design. Simulation has to be corrected by SoC designs (as in "functional" verification), but many subtle design errors can not be caught by simulation. Recently, formal verification, giving a mathematical proof of correctness, has been getting much more attention. So far, most of the books on formal verification. Transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be very much more than RTL. This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs.

. Above all, the design verification targeting SoC designs.
. Formal verification of high-level designs (RTL or higher).
. Verification techniques are discussed with associated system-level design methodology.