Cmod S7 - module with Spartan-7 FPGA
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  • Cmod S7 - module with Spartan-7 FPGA
  • Cmod S7 - module with Spartan-7 FPGA
  • Cmod S7 - module with Spartan-7 FPGA
ID: 575970
zł480.35
Tax included

zł390.53 tax excl.

DIP module with 36 pins, based on the Xilinx Spartan-7 FPGA chip. Provides 32 digital I/O signals and 2 analog input signals. The pins are spaced 100 miles (2.54 mm), making Cmod S7 perfect for use with breadboards. Digilent Cmod S7

24h
Available
Available quantity: 1
 

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14 days for return

Each consumer can return the purchased goods within 14 days

Description

The Digilent Cmod S7 is a small, 48-pin DIP form factor board populated with 36 pins and built around a Xilinx Spartan-7 FPGA. The 32 FPGA digital I/O signals, 2 FPGA analog input signals, an external power input rail, and ground are routed to 100-mil-spaced through-hole pins, making the Cmod S7 well-suited for use with solderless breadboards. At just 0.7” by 3.05” inches, it can be loaded in a standard socket and used in embedded systems. The board also includes a programming ROM, clock source, USB programming and data transfer circuit, power supplies, LEDs, and buttons.

Digilent Cmod S7 can be configured in several ways:

  • from a PC via the built-in USB programming circuit
  • from an external programmer connected to the 6-pin JTAG connector
  • from the built-in Quad-SPI flash memory

Configuration files can be prepared using Xilinx’s ISE 14.2 (or newer) software, using the "Digilent’s Adept system" or using older versions of Xilinx tools. The Xilinx’s ISE / Impact or Digilent’s Adept software should recognize the board and FPGA connected to the PC using a USB cable.

Xilinx’s iMPACT tool and Digilent’s Adept can be used to program FPGA and embedded Quad-SPI Flash memory. The documentation contains information on software and configuration.

Features

  • Xilinx Spartan-7 FPGA (XC7S25-1CSGA225C)
    • 3,650 slices containing four 6-input LUTs and 8 flip-flops
    • 1,620 Kbits of fast block RAM
    • Three clock management tile, each with a phase-locked loop and mixed-mode clock manager
    • 80 DSP slices
    • Internal clock speeds exceeding 450 MHz
    • On-chip analog-to-digital converter (XADC)
    • Programmable over JTAG and Quad-SPI Flash
  • Memory
    • 4 MB Quad-SPI Flash
  • Power
    • Powered from USB or 5V external supply connected to DIP pin 24 (micro USB cable NOT included)
  • USB
    • USB-JTAG programming circuitry
    • USB-UART bridge
  • Push-buttons and LEDs
    • 2 Buttons
    • 4 LEDs
    • 1 RGB LED
  • Expansion Connectors
    • 1 Pmod connector
      • 8 total FPGA I/O
    • 48-pin DIP form-factor headers
      • 36 populated pins
        • 32 total FPGA I/O
        • 2 Single-ended 0-3.3V analog inputs to XADC
575970

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