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Basys3 is an entry-level FPGA board designed exclusively for the Vivado Design Suite, featuring Xilinx Artix 7-FPGA architecture. 410-183
ATTENTION! This product is for academic recipients (students and academic teachers) only!
After the ordering, please send us by e-mail the data listed below:
- the name and last name
- position (student, teacher)
- e-mail (with the University domain)
- University name
- Facultie / Section
- University address
- University phone no.
- Notice! Students must send a copy of University Identity Card (by e-mail)
The Basys 3 is an entry-level FPGA development board designed exclusively for the Vivado® Design Suite featuring the Xilinx® Artix®-7-FPGA architecture. Basys 3 is the newest addition to the popular Basys line of FPGA development boards for students or beginners just getting started with FPGA technology. The Basys 3 includes the standard features found on all Basys boards: complete ready-to-use hardware, a large collection of on-board I/O devices, all required FPGA support circuits, and a free version of development tools and at a student-level price point.
The Basys 3 does not ship with a USB cable.
Double the user interface switches, double the number of onboard outputs, upgraded the number of external ports (moving from 6-pin single-row Pmods to 12-pin double-row Pmods) and included for the first time on a Basys class device a USB-UART bridge.
Due to the migration from the Spartan®-3E family to the Artix-7 class of device, the Basys 3 offers a substantial increase in hardware capabilities. With the new Artix FPGA comes 15X the logic cells (from 2,160 to 33,280) and the upgrade from multipliers to true DSP slices. It also adds over 26X the amount of RAM.
Industry's First SOC Strength Design Suite:
The most significant change to the Basys 3 is the upgrade to Xilinx Vivado® Design Suite, the most modern design tool chain used by professional engineers worldwide. Compared to ISE®, Vivado offers an improved user experience and expanded capabilities. These capabilities include block-based IP integration (which can reduce development time up to 10x) and the Vivado Logic/Serial I/O analyzer*.
* Only available with Vivado Design Edition - Additional Documentation can be found on the Digilent Wiki Site for Basys3.
Device/IC: Xilinx Artix-7 FPGA (XC7A35T-1CPG236C)
Programming: Designed exclusively for the Vivado Design Suite