Terasic DE0-Nano [EDU] - zestaw startowy z układem FPGA z rodziny Cyclone IV firmy Altera
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  • Terasic DE0-Nano [EDU] - zestaw startowy z układem FPGA z rodziny Cyclone IV firmy Altera
ID: 180093
zł569.26
Tax included

zł462.81 tax excl.

Altera DE0 NANO Development and Education Board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 LEs.

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Available quantity: 1


ATTENTION! This product is for academic recipients (students and academic teachers) only!

After the ordering, please send us by e-mail the data listed below:

  • the name and last name
  • position (student, teacher)
  • e-mail (with the University domain)
  • University name
  • Facultie / Section
  • University address
  • University phone no.
  • End user application

Description

The DE0-Nano board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 LEs.

The DE0-Nano has a collection of interfaces including two external GPIO headers to extend designs beyond the DE0-Nano board, on-board memory devices including SDRAM and EEPROM for larger data storage and frame buffering, as well as general user peripheral with LEDs and push-buttons.

The advantages of the DE0-Nano board include its size and weight, as well as its ability to be reconfigured without carrying superfluous hardware, setting itself apart from other general purpose development boards. In addition, for mobile designs where portable power is crucial, the DE0-Nano provides designers with three power scheme options including a USB mini-AB port, 2-pin external power header and two DC 5V pins.

Features

Cyclone® IV EP4CE22F17C6N FPGA

  • 22,320 Logic elements (LEs)
  • 594 Embedded memory (Kbits)
  • 66 Embedded 18 x 18 multipliers
  • 4 General-purpose PLLs
  • 153 Maximum FPGA I/O pins 

Configuration Status and Set-Up Elements

  • On-board USB-Blaster circuit for programming
  • Altera serial configuration device – EPCS16

Expansion Header

  • Two 40-pin Headers (GPIOs) provides 72 I/O pins
  • Two 5V power pins, two 3.3V power pins and four ground pins
  • One 26-pin header provides 16 digital I/O pins and 8 analog input pins to connect to analog sensors, etc 

Memory Devices

  • 32MB SDRAM
  • 2Kb I2C EEPROM 

General User Input/Output

  • 8 green LEDs
  • 2 debounced push-buttons
  • 4 dip switches 

G-Sensor

  • ADI ADXL345, 3-axis accelerometer with high resolution (13-bit) 

A/D Converter

  • NS ADC128S022, 8-Channel, 12-bit A/D Converter

  • 50 ksps to 200 ksps 

Clock System

  • On-board 50MHz clock oscillator

Power Supply

  • USB Type mini-AB port (5V)
  • Two DC 5V pins of the GPIO headers (5V)
  • 2-pin external power header (3.6-5.7V)

Connectivity:

Connect D5M

  • Connect with 5-megapixel CMOS Sensor (D5M)

Connect LTM

  • Connect with LCD Touch Screen Module (LTM)  

Connect THDB-ADA

  • Connect with Analog to Digital/Digital to Analog Conversion Daughter Card (THDB-ADA)

     

Layout

DE0-Nano Control Panel

  • Allows users to access various components on the DE0-Nano board from a host computer.

   

DE0-Nano System Builder

  • This tool will allow users to create a Quartus II project on their custom design for the DE0-Nano board with the top-level design file, pin assignments, and I/O standard settings automatically generated.

Kit Contents

The DE0-Nano package includes:

Download

180093

Manufacturer BTC Korporacja sp. z o. o. Lwowska 5 05-120 Legionowo Poland sprzedaz@kamami.pl 22 767 36 20

Responsible person BTC Korporacja sp. z o. o. Lwowska 5 05-120 Legionowo Poland sprzedaz@kamami.pl 22 767 36 20

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