TerasIC 16X2 LCD Module (No Backlight)

The Terasic DE25-Nano development board with Agilex™ 5 FPGA and ARM Cortex-A76/A55 HPS system is a modern platform for AI applications, vision processing, and embedded systems. A rich set of interfaces and memory, active cooling, and compact dimensions allow it to be used both in prototyping and in final industrial solutions.

TerasIC SDI HSMC is a specialized module for FPGA projects in the field of video transmission, offering support for SDI and AES standards and full compatibility with HSMC platforms. It is ideal for developing broadcasting solutions, signal analyzers, and professional video applications.

The DE10-Standard Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. P0493

Development platform based on Intel MAX 10 FPGA. The system provides the user with 50,000 logical elements and 1638 kbits M9K and 5888 kbits Flash. The board contains components such as embedded USB-Blaster II, QSPI Flash, ADC connector, WS2812B RGB LED and 2x6 TMD connector. TerasiC T-Core P0633

The Terasic VEEK-MT2 set provides a complete hardware-software platform for designing embedded and multimedia systems using FPGA chips. It enables the creation and testing of interactive, control, and measurement applications thanks to an extensive base of interfaces, memory, and sensors.

SoM module with SoC connecting the FPGA with the ARM Cortex-A9 core. The board is equipped with DDR4 Eadge connector (with 3.3 V power supply). P0553

FPGA starter kit with Intel Stratix 10 SX chip. The module has integrated transceivers that transmit data at speeds up to 28.3 Gb/s, making DE10-Pro fully compatible with version 3.0 of the PCI Express standard. The DE10-Pro offers fast parallel Flash memory and four SO-DIMMs that have 4 GB DDR4 SDRAM. Terasic P0627

Programmable Logic IC Development Tools Cyclone V SE 5CSEMA4U23C6N + 800MHz Dual-core ARM Cortex-A9 processor. Terasic P0496

The TerasIC HDMI_TX P0084 module enables HDMI transmission using the HSMC interface in FPGA projects. Compatibility with the latest HDMI standards and the provided source code accelerate the development and testing of vision and multimedia applications in FPGA-based systems.

The TerasIC HDMI v1.4 (P0087) module enables the implementation of a complete HDMI transmit–receive chain in FPGA systems. With support for Full HD resolution, compliance with HDMI 1.4a, and included reference designs, it serves as a versatile solution for testing, learning, and deploying video transmission in embedded and multimedia applications.

Compact FPGA kit with Intel Arria 10 GX chip equipped with 8 GB DDR4-2133 memory and Thunderbolt 3 communication connector. Can be used directly on laptops or other portable devices. Academic version. Terasic FLIK P0642

TerasIC USB Blaster Download Cable (UBT) is a fully Altera USB Blaster–compatible JTAG/ISP programmer for CPLD and FPGA devices. With a reliable design and resistance to interference, it is a universal tool for designers working with Altera programmable devices. TerasIC P0302

Development platform based on Intel MAX 10 FPGA. The system provides the user with 50,000 logical elements and 1638 kbits M9K and 5888 kbits Flash. The board contains components such as built-in USB-Blaster II, QSPI Flash, ADC connector, WS2812B RGB LED and 2x6 TMD connector. Academic version. TerasiC T-Core P0633

The robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system.

Altera DE0 NANO Development and Education Board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 LEs.