Right Angle (RAFF) Adapter (8.06.32)

An adapter that allows you to connect a 20-pin 0.1" connector to a 10-pin connector, allowing you to easily connect J-Link or Flasher programmers to your PCB using through-wires. It is ideal for prototyping, testing new designs and working with ST Discovery boards, offering flexibility, speed and time savings when making design changes.Segger Flying Wire Adapter (06.08.27)

An adapter that converts a standard 20-pin 2.54 mm connector to a 10-pin 2.54 mm connector. It enables the connection of Segger programmers with Silicon Labs devices and development boards with a C2 interface. Segger SiLabs C2 Adapter (8.06.17)

J-Link 6-pin Needle Adapter (8.06.16)

J-Link RX Adapter, RoHS, Segger

A device that provides electrical isolation between the J-Trace emulator and the ARM board, which protects against electrical interference, especially in systems where the development tools and the application do not share the same ground. It provides 1 kV DC isolation, supports trace frequencies up to 75 MHz, and is compatible with J-Trace V2 and later versions, with a minimum power consumption of 25 µA. Segger J-Trace Isolator (07/08/10)

Compact evaluation board for testing NOR and NAND flash memory supported by emFile drivers. Enables fast and reliable flash programming with SEGGER tools, offering support for various packages such as SO-8, SO-16, BGA and SON. SEGGER (Q)SPI Flash Evaluator (6.40.00)

Adapter that converts standard 20-pin 2.54 mm connector to SWIM connector and 10-pin connector. Used for programming STM8 chips. Segger STM8 Adapter (8.06.22)

Power adapter providing a stabilized 5V supply voltage for the target board. Segger 5V Target Supply Adapter (8.06.29)

The Intel FPGA Adapter (formerly J-Link Altera Adapter) connects to the Intel FPGA 10-pin JTAG connector, enabling debugging of FPGA-based MCU cores such as the dual-core Arm Cortex-A9 in Cyclone V devices. on Intel FPGA solutions.

A set of three adapters for SO-8, SO-8W and SO-16 memories that allows easy testing and programming of flash devices in these packages, eliminating the need for dedicated solutions for each form factor. The adapters are compatible with the SEGGER (Q)SPI Flash Evaluator and other test systems, making them a versatile tool for both test and production. SEGGER (Q)SPI Flash Evaluator Adapter Board Pack for SO-8, SO-8W, SO-16 (6.40.01)

The Segger J-Link Supply Adapter (8.06.14) allows you to manually set the debug probe I/O voltage, preventing damage to the target board, adjustable from 1.2V to 5.0V. It can be inserted between J-Link or Flasher and the target device, reducing the number of connections needed, which is especially useful in a production environment.

A compact reference platform that enables rapid testing and verification of trace configurations, providing excellent signal quality for analysis. With the ST STM32H743 microcontroller and support for JTAG, SWD and SWO debugging interfaces, the board provides high performance and flexibility in monitoring system performance. Segger STM32H7 Trace Reference Board (6.68.20)

Adapter enabling easy connection of a Microchip AVR microcontroller device with the SEGGER Flasher programming system, supporting 6-pin and 10-pin connectors and providing fast connection via SPI protocol. With the function of powering the target hardware (3.3V or 5V) and direct power supply via VTREF connection, the adapter is flexible, easy to use and ideal for programming and debugging AVR microcontrollers in embedded systems, providing reliable communication and high precision. Segger AVR SPI Adapter (8.06.25)

Segger adapter 8.06.28 allows conversion from a 20-pin 0.1" connector to a 10-pin 0.05" Cortex-M type connector with the option of custom pin mapping. A useful solution for integrating programmers and debuggers with devices featuring different pin configurations.

Adapter from the standard 20-pin 2.54 mm connector to the 10-pin 1.27 mm connector often used in Cortex-M boards. Segger 50-Mil 10-Pin Patch Adapter (8.06.28)

The Segger J-Link Signal Smoothing Adapter (8/06/12) is designed to improve signal integrity between the J-Link debug probe and the target debug device. It allows JTAG signals to be suppressed by adjustable series resistors, preventing excessive gain and jitter.