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New products
New products
Virtex-5 OpenSPARC Evaluation Platform
The Virtex-5 OpenSPARC Evaluation Platform is a powerful system for hosting the OpenSparc T1 open-source microprocessor. Based on the Xilinx XUPV5-LX110T, a versatile general purpose development board powered by the Virtex -5 FPGA, this kit brings the throughput of OpenSPARC Chip Multi-Threading to an FPGA.
Kit Includes:
- XUPV5-LX110T board
- 1GB Compact Flash card
- 256 MB SODIMM module
- SATA cable
- Platform USB programming cable
- DVI to VGA adapter
- 6A power supply
OpenSPARC T1 is the open-sourced version of the custom designed UltraSPARC T1 Microprocessor from Sun Microsystems. To broaden the appeal of this state-of-the-art Chip Multi-threading (CMT) technology to the developers, engineers at Sun Microsystems and Xilinx Inc. have developed a reference design that allows a scaled-down version of the OpenSPARC T1 processor to run on Xilinx Virtex 5 FPGAs. We believe this reference design will be an excellent starting point for researchers and entrepreneurs to build and test novel ideas in the areas of computer architecture, logic design, parallel programming, and compiler techniques, among others. For more details on how to download the OpenSPARC design and the reference design, please visit www.opensparc.net/fpga
For documentation and reference designs, please visit http://www.xilinx.com/univ/xupv5-lx110t.htm
For more information and to learn more about bringing Sun's OpenSPARC program to your university, please visit www.opensparc.net/edu/university-program.html
Key Features:
- Xilinx Virtex-5 XC5VLX110T FPGA
- Two Xilinx XCF32P Platform Flash PROMs (32 Mbyte each) for storing large device configurations
- Xilinx SystemACE Compact Flash configuration controller
- 64-bit wide 256Mbyte DDR2 small outline DIMM (SODIMM) module compatible with EDK supported IP and software drivers
- On-board 32-bit ZBT synchronous SRAM and Intel P30 StrataFlash
- 10/100/1000 tri-speed Ethernet PHY supporting MII, GMII, RGMII, and SGMII interfaces
- USB host and peripheral controllers
- Programmable system clock generator
- Stereo AC97 codec with line in, line out, headphone, microphone, and SPDIF digital audio jacks
- RS-232 port, 16x2 character LCD, and many other I/O devices and ports
Code: 6003-410-006
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collective work, M. Rezulski (ed.)
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