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New products
New products
zł3,106.99 tax excl.
[EDUCATIONAL PRICE] FPGA starter kit equipped with Cyclone V GT with 301K LE and supports PCIe Gen 2x4. The board has 1 GB DDR3 memory, 64 MB SDRAM memory, UART-USB interface and extensions such as GPIO and Arduino. Terasic P0559
Free shipping
free shipping in Poland for all orders over 500 PLN
Same day shipping
If your payment will be credited to our account by 11:00
14 days for return
Each consumer can return the purchased goods within 14 days
ATTENTION! This product is for academic recipients (students and academic teachers) only!
After the ordering, please send us by e-mail the data listed below:
- the name and last name
- position (student, teacher)
- e-mail (with the University domain)
- University name
- Facultie / Section
- University address
- University phone no.
- End user application
Description
OpenVINO is a high performance PCIe based FPGA starter kit. It is equipped with Cyclone V GT with 301K LE and supports PCIe Gen 2x4. The board has 1 GB DDR3 memory, 64 MB SDRAM memory, UART-USB interface and extensions such as GPIO and Arduino. This makes the OpenVINO starter kit a configurable platform combining high computing performance and low energy consumption.
The OpenVINO package contains reference projects for all peripherals of the set and detailed instructions for programmers.
Features
- FPGA Device (Cyclone V)
- 301K Programmable Logic Elements
- 13,917 Kbits embedded memory
- Eight Fractional PLLs
- Two Hard Memory Controllers
- Nine Transceivers (the GT speed is 6.144G, and GX speed is 3.125G )
- Configuration and Debug
- Quad Serial Configuration device-EPCQ256
- On-Board USB Blaster II (Mini-B USB connector)
- Memory Device
- 64MB (32M x16) SDRAM
- 1GB (2 x256M x16) DDR3 SDRAM
- Communication
- UART to USB(Mini-B USB connector)
- GT device supports PCIe Gen2x 4(GX device supports PCIe Gen1x 4)
- Expansion I/O
- 36 General GPIO Pins
- Support 8 pairs LVDS TX and 8 pairs LVDS RX
- Diode protection circuit
- Configurable I/O standards: 1.5/1.8/2.5/3.3V
- 2 x40 GPIO Header
- One Arduino Uno Revision 3 Expansion HearderSMA IN/OUT 3.3V single port
- Analog ADC
- SPI Interface
- 500Ksps Sampling Rate
- Eight Channels
- 12-Bit Resolution
- Analog Input Range:0 ~ 4.096 V
- Resolution: 12-bit
- Digital IO
- Diode protection circuit
- Switches, Buttons, LED, and 7-Segments
- 5 User Buttons (4 normal buttons, one CPU_RESET_n)
- 4 User Switches
- 4 LEDs
- 2 7-Segments
- Power
- 12V DC input
- PCIe 12V Input
- Cooling
- 12V, 5000 Speed Fan
- Dimensions: 167.6 x 83.2 mm
Description of connectors
Block diagram
Kit contains
- OpenVINO Starter Kit Development Board
- OpenVINO Starter Kit Quick Start Guide
- PCIe Bracket (Installed)
- Fan (Installed)
- Screw and Silicon Footstands Package
- AC Power Cord
- Power Adapter
USB to miniUSB Cable
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FPGA starter kit equipped with Cyclone V GT with 301K LE and supports PCIe Gen 2x4. The board has 1 GB DDR3 memory, 64 MB SDRAM memory, UART-USB interface and extensions such as GPIO and Arduino. Terasic P0559
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[EDUCATIONAL PRICE] FPGA starter kit equipped with Cyclone V GT with 301K LE and minicomputer with Intel Celeron Dual Core (64 GB eMMC, 4 GB RAM). The FPGA module has 1 GB DDR3 memory, 64 MB SDRAM memory, UART-USB interface and extensions such as GPIO and Arduino. Terasic P0650
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FPGA starter kit equipped with Cyclone V GT with 301K LE and minicomputer with Intel Celeron Dual Core (64 GB eMMC, 4 GB RAM). The FPGA module has 1 GB DDR3 memory, 64 MB SDRAM memory, UART-USB interface and extensions such as GPIO and Arduino. Terasic P0650
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Altera DE0 NANO Development and Education Board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 LEs.
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Development platform based on Intel MAX 10 FPGA. The system provides the user with 50,000 logical elements and 1638 kbits M9K and 5888 kbits Flash. The board contains components such as embedded USB-Blaster II, QSPI Flash, ADC connector, WS2812B RGB LED and 2x6 TMD connector. TerasiC T-Core P0633
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The DE10-Standard Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. P0493
The robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system.
Programmable Logic IC Development Tools Cyclone V SE 5CSEMA4U23C6N + 800MHz Dual-core ARM Cortex-A9 processor. Terasic P0496
Computation accelerator module based on Intel® Agilex ™ FPGA. It has a PCI Express Gen 4.0 x16 slot, two 200G QSFP-DD connectors, and offers 32GB DDR4. Terasic DE10-Agilex (P0701)
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Compact FPGA kit with Intel Arria 10 GX chip equipped with 8 GB DDR4-2133 memory and Thunderbolt 3 communication connector. Can be used directly on laptops or other portable devices. Academic version. Terasic FLIK P0642
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Set with FPGA Terasic DE10-Nano board and WiFi module. Designed for projects using FPGA to work in the cloud. TerasIC P0700
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